1. Field of the Invention
This invention relates to, for example, a static random access memory (hereinafter, referred to as SRAM), and more particularly to an on-chip semiconductor memory device used in a microprocessor or the like.
2. Description of the Related Art
In recent years, to meet a demand for system performance enhancement, system LSIs, such as microprocessors, have been speeded up. In parallel with this, the SRAM embedded in the system SLI has also been required to operate at high operating frequency.
The cell array of an SRAM has been divided into sub-arrays. The bit lines are composed of the local bit lines in each sub-array and the global bit lines shared by the sub-arrays. Hierarchizing the bit lines this way makes it possible to reduce the load on the bit lines required to charge and discharge in one cycle of the clock signal, which enables a high-speed operation.
As an SRAM of this type, the technique for preventing an increase in the number of bit lines per cell has been developed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 2002-100187). Moreover, to reduce the chip area, a semiconductor memory device which has a hierarchic bit line structure with a decreased number of global bit lines has been developed (for example, refer to Jpn. Pat. Appln. KOKAI Publication No. 10-308089).
However, when the bit lines are hierarchized, the operating frequency of the SRAM is determined by the operating frequency of a global bit line with a high load, not by the operating frequency of the memory access in the sub-array. For this reason, it is difficult to increase the operating frequency remarkably.
Furthermore, another type of SRAM has been developed. The SRAM, which does not use a hierarchic bit line structure, causes transfer gates connected between a pair of nodes and a pair of bit lines which memorize complementary data in a memory cell to operate in different phases of the clock signal. The SRAM operates as follows. In the first half of one cycle of the clock signal, the word line for the transfer gate connected to one bit line is activated, with the result that the data read from the selected cell is supplied to the one bit line. Then, in the latter half of the one cycle of the clock signal, the word line for the transfer gate connected to the other bit line is activated, with the result that the data read from the selected cell is supplied to the other bit line. The data read onto the respective bit lines are selected and output alternately according to the phase of the clock signal. In this example, the throughput of read-out data from the SRAM can be doubled by changing the phase of the clock signal used to access a pair of complementary bit lines. Therefore, the SRAM operates as if the operating frequency were doubled. However, since a pair of transfer gates is selected alternately, each memory cell has to be provided with two word lines. Accordingly, in the SRAM, the area occupied by the memory cells becomes large, which causes the problem of increasing the area of the entire SRAM. Therefore, there has been a need for a semiconductor memory device capable of a high-speed operation at a high operating frequency, while suppressing an increase in the cell area.